Preliminary

PLL520-20

Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 6

PAD ASSIGNMENT

Pad #

Name

X (

µm)

Y (

µm)

1

GND

248

109

2

GND

361

109

3

GND

473

109

4

GND

587

109

5

GND

702

109

6

N/C

874

109

7

GND

1042

109

8

GNDBUF

1171

109

9

OE_SELECT

1400

125

10

LVDS

1400

259

11

PECL

1400

476

12

VDDBUF

1400

616

13

VDDBUF

1400

716

14

PECLB

1400

871

15

LVDSB

1400

1089

16

CMOS

1400

1227

17

GNDBUF

1389

1365

18

OUTSEL1

1232

1365

19

DNC (Do Not Connect)

1042

1365

20

DNC (Do Not Connect)

854

1365

21

VDD

659

1365

22

VDD

559

1365

23

VDD

459

1365

24

VDD

358

1365

25

OUTSEL0

194

1365

26

XIN

109

1223

27

XOUT

109

1017

28

DNC (Do Not Connect)

109

858

29

DNC (Do Not Connect)

109

646

30

OE_CTRL

109

397

31

VCON

109

181

Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.