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MTC20455 Arkusz danych(PDF) 15 Page - STMicroelectronics

Numer części MTC20455
Szczegółowy opis  QUAD ADSL DMT TRANSCEIVER
PDF  23 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MTC20455 Arkusz danych(HTML) 15 Page - STMicroelectronics

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MTC20455
Figure 7. ATM Specific TC Layer Functions
DMT Symbol Timing Unit (DSTU)
The DSTU interfaces with various modules, like DSP Front-End, FFT/IFFT, Mapper/Demapper, RS, Mon-
itor and Transceiver Controller. It consists of a real time and a scheduler module. The real time unit gen-
erates a time-base for the DMT symbols (sample counter), superframes (symbol counter) and
hyperframes (sync counter). The timebases can be modified by various control features. They are contin-
uously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program
opcodes and a set of variables, the most important of which are real time counters. The transmit and re-
ceive sequencers are completely independent and run different programs. An independent set of variables
is assigned to each of them. The sequencer programs can be updated in real time.
Interface Module
The interface module collects cells (from the cell-based function module) or a byte stream (from the de-
framer). Cells are stored in FIFO’s (424 bytes or 8 cells wide, transmit buffers have the same size), from
which they are extracted by the interface submodule, providing an Utopia level 2 interface.
Analog Front-End Control Interface
The Analog Front-End Interface is designed to be connected to the MTC20154 or MTC20454 Analog
Front-End component Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As
a result 4 cycles are needed to transfer 1 word. Refer to Table 10 for the bit/pin allocation for the 4 cycles.
The first of 4 cycles is identified by the CLWD signal (Fig.7). The Analog Front-End fetches the 16 bit word
to be multiplexed on AFTXD from the Tx Digital Front-End module.
Table 10. Bits assigned to pins/time slot for single line interface
Cycle 0
Cycle 1
Cycle 2
Cycle 3
AFRXD_i[0]
b0
b4
b8
b12
AFRXD_i[1]
b1
b5
b9
b13
AFRXD_i[2]
b2
b6
b10
b14
AFRXD_i[3]
b3
b7
b11
b15
GP_IN
t0
t1
t2
t3
From Generic TC
FAST
SLOW
To Interface
Module
Cell
Descrambler
Synchronizer
HEC
Cell filter
Cell
Descrambler
Synchronizer
HEC
Cell filter
BER
BER



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