MTC20455

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Table 11. Bits assigned to pins/time slot for muxed-line interface

Receive Interface

The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to trans-

fer 1 word. Refer to Table 11 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by

the CLWD signal. (Fig.9). The CLWD must repeat after 4 MCLK cycles.

Figure 8. Receive word timing diagram for single line Interface

Figure 9. Receive word timing diagram for muxed line interface

Table 12. Transmitted bits assigned to signal/time slot for single-line interface

Cycles

01

23456789

10

11

12

13

14

15

line 0

line 1

line 2

line 3

line 0

line 1

line 2

line 3

AFRXD_1[0]

b0

b4

b0

b4

b0

b4

B0

b4

b8

b12

b8

b12

b8

b12

b8

b12

AFRXD_1[1]

b1

b5

b1

b5

b1

b5

b1

b5

b9

b13

b9

b13

b9

b13

b9

b13

AFRXD_1[2]

b2

b6

b2

b6

b2

b6

b2

b6

b10

b14

b10

b14

b10

b14

b10

b14

AFRXD_1[3]

b3

b7

b3

b7

b3

b7

b3

b7

b11

b15

b11

b15

b11

b15

b11

b15

Cycle 0

Cycle 1

Cycle 2

Cycle 3

AFTXD_I[0]

b0

b4

b8

b12

AFTXD_I[1]

b1

b5

b9

b13

AFTXD_I[2]

b2

b6

b10

b14

AFTXD_I[3]

b3

b7

b11

b15

POWER_DOWN_i

t0

t1

t2

t3

Cycle0

Cycle1

Cycle2

Cycle3

CLWD_i

AFRXD_i

MCLK_i

test0

test1

test

test3

GP_IN

Cycle

CLWD_1

MCLK_1

AFRXD_1

0123456

7

9

10

11

12

13

14

15

8

line 0

line 1

line 2

line 3

line 0

line 1

line 2

line 3

1