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STM32L072CZ Arkusz danych(PDF) 105 Page - STMicroelectronics |
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STM32L072CZ Arkusz danych(HTML) 105 Page - STMicroelectronics |
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105 / 160 page  DS10689 Rev 5 105/160 STM32L072xx Electrical characteristics 122 Figure 31. Typical connection diagram using the ADC 1. Refer to Table 64: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 32 or Figure 33, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA) MSv34712V1 VDDA AINx IL±50nA VT RAIN(1) Cparasitic VAIN VT RADC 12-bit converter CADC Sample and hold ADC converter MS39601V1 VREF+ STM32Lxx VDDA VSSA / VREF– 1 μF // 100 nF 1 μF // 100 nF |
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