STA369BWS datasheet(45/92 Pages) STMICROELECTRONICS

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STA369BWS

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

LRCK double trigger protection

LDTE, when enabled, prevents double trigger of LRCLK on instable I2S input.

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

IC power down

Table 45. Invalid input detect mute enable

Bit

R/W

RST

Name

Description

R/W

IDE

0: disables the automatic invalid input detect mute

1: enables the automatic invalid input detect mute

Table 46. Binary output mode clock loss detection

Bit

R/W

RST

Name

Description

R/W

BCLE

0: binary output mode clock loss detection disabled

1: binary output mode clock loss detection enable

Table 47. LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

0: LRCLK double trigger protection disabled

1: LRCLK double trigger protection enabled

Table 48. Auto EAPD on clock loss

Bit

R/W

RST

Name

Description

R/W

ECLE

0: auto EAPD on clock loss not enabled

1: auto EAPD on clock loss

Table 49. IC power down

Bit

R/W

RST

Name

Description

R/W

PWDN

0: IC power down low-power condition

1: IC normal operation

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