AD9161BBCZ datasheet(58/144 Pages) AD

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AD9161/AD9162

Data Sheet

Rev. D | Page 58 of 58

TRANSPORT LAYER

DELAY

BUFFER 1

DELAY

BUFFER 0

F2S_0

F2S_1

DAC A_I0[15:0]

DAC A_Q0[15:0]

PCLK_1

LANE 0 OCTETS

LANE 7 OCTETS

PCLK_0

SPI CONTROL

LANE 3 OCTETS

LANE 4 OCTETS

DAC B_I0[15:0]

DAC B_Q0[15:0]

TRANSPORT LAYER

(QBD)

SPI CONTROL

PCLK_0

PCLK_1

FIFO

Figure 160. Transport Layer Block Diagram

The transport layer receives the descrambled JESD204B frames

and converts them to DAC samples based on the programmed

JESD204B parameters shown in Table 24. The device parameters

are defined in Table 25.

Table 24. JESD204B Transport Layer Parameters

Parameter

Description

Number of octets per frame per lane: 1, 2, or 4

Number of frames per multiframe: K = 32

Number of lanes per converter device (per link), as

follows: 4, or 8

Number of converters per device (per link), as follows:

1 or 2 (2 is used for complex data interface)

Number of samples per converter, per frame: 1 or 2

Table 25. JESD204B Device Parameters

Parameter

Description

Number of control words per device clock per link.

Not supported, must be 0.

Number of control bits per conversion sample. Not

supported, must be 0.

High density user data format. Used when samples

must be split across lanes.

Set to 1 always, even when F does not equal 1.

Otherwise, a link configuration error triggers and

the IRQ_ILAS flag is set.

Converter resolution = 16.

N' (or NP)

Total number of bits per sample = 16.

Certain combinations of these parameters are supported by the

AD9161/AD9162. See Table 28 for a list of supported

interpolation rates and the number of lanes that is supported for

each rate. Table 28 lists the JESD204B parameters for each of the

interpolation and number of lanes configuration and gives an

example lane rate for a 5 GHz DAC clock. Table 27 lists

JESD204B parameters that have fixed values. A value of yes in

Table 26 means the interpolation rate is supported for the number

of lanes. A blank cell means it is not supported.

Table 26. Interpolation Rates and Number of Lanes

Interpolation

1×

Yes1

2×

Yes

Yes1

3×

Yes

4×

Yes

Yes1

6×

Yes

8×

Yes

12×

Yes

16×

Yes

24×

Yes

1 These modes restrict the maximum DAC clock rate to 5 GHz.

Table 27. JESD204B Parameters with Fixed Values

Parameter

Value

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