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34AA02 Arkusz danych(PDF) 8 Page - Microchip Technology

Numer części 34AA02
Szczegółowy opis  2-Kbit I2C Serial EEPROM Software Write-Protect
PDF  40 Pages
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Producent  MICROCHIP [Microchip Technology]
Strona internetowa  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

34AA02 Arkusz danych(HTML) 8 Page - Microchip Technology

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34AA02/34LC02
DS20002029G-page 8
 2007-2022 Microchip Technology Inc. and its subsidiaries
3.0
FUNCTIONAL DESCRIPTION
The 34XX02 has two Software Write-Protect features
that allow the user to protect half of the array from being
written (Addresses 00h-7Fh). One command, Software
Write-Protect (SWP) will prevent writes to half of the
array and is resettable by using the Clear Software
Write-Protect (CSWP) command. The other command
is Permanent Software Write-Protect (PSWP), which is
not resettable and will permanently lock half the array
from being written to. The device still has an external
pin (WP) that allows the user to protect the entire array
if so desired.
The 34XX02 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data, as a receiver. The bus has to be con-
trolled by a host device, which generates the Serial
Clock (SCL), controls the bus access and generates
the Start and Stop conditions, while the 34XX02 works
as client. Both host and client can operate as transmit-
ter or receiver, but the host device determines which
mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal. The data
on the line must be changed during the low period of
clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop condi-
tions is determined by the host device and is, theoreti-
cally, unlimited; although only the last 16 bytes will be
stored when doing a write operation. When an over-
write does occur, it will replace data in a First-In
First-Out (FIFO) principle.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. Exceptions to this rule relating to software write
protection are described in Section 7.0 “Write Protec-
tion”. The host device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the Acknowledge-related clock pulse.
Moreover, setup and hold times must be taken into
account. During reads, a host must signal an
end-of-data to the client by not generating an
Acknowledge bit on the last byte that has been clocked
out of the client. In this case, the client (34XX02) will
leave the data line high to enable the host to generate
the Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 34XX02 does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition



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