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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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RZ/A Arkusz danych(PDF) 28 Page - Renesas Technology Corp |
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RZ/A Arkusz danych(HTML) 28 Page - Renesas Technology Corp |
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28 / 83 page  RZ Family / RZ/G, RZ/A Series 2. Functional Specifications R01UH0990EJ0101 Rev.1.01 Page 28 of 83 Jul 28, 2022 Table 2.2 List of Pin Function Selection Used on Each Module Board (4/18) Pin Location Pin Name RZ/G2UL Pin Function RZ/A3UL Pin Function RZ/Five Pin Function Description SMARC Pin No. SMARC Pin Name V24 DDR_DQS0_N DDR_DQS0_N DDR_DQS0_N DDR_DQS0_N DDR4 SDRAM (IC7) — — V25 DDR_DQS0_P DDR_DQS0_P DDR_DQS0_P DDR_DQS0_P DDR4 SDRAM (IC7) — — AB25 DDR_DQS1_N DDR_DQS1_N DDR_DQS1_N DDR_DQS1_N DDR4 SDRAM (IC7) — — AB24 DDR_DQS1_P DDR_DQS1_P DDR_DQS1_P DDR_DQS1_P DDR4 SDRAM (IC7) — — M24 DDR_ODT0 DDR_ODT0 DDR_ODT0 DDR_ODT0 DDR4 SDRAM (IC7) — — L25 DDR_ODT1 DDR_ODT1 DDR_ODT1 DDR_ODT1 DDR4 SDRAM (IC7) — — H24 DDR_RAS# DDR_RAS# DDR_RAS# DDR_RAS# DDR4 SDRAM (IC7) — — B23 DDR_RESET# DDR_RESET# DDR_RESET# DDR_RESET# DDR4 SDRAM (IC7) — — H20 DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR4 SDRAM (IC7) — — K20 DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR4 SDRAM (IC7) — — M20 DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR4 SDRAM (IC7) — — R20 DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR4 SDRAM (IC7) — — U20 DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR4 SDRAM (IC7) — — W20 DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR_VDDQ DDR4 SDRAM (IC7) — — G25 DDR_WE# DDR_WE# DDR_WE# DDR_WE# DDR4 SDRAM (IC7) — — Y19 DEBUGEN DEBUGEN DEBUGEN DEBUGEN DIP_SW (SW1) — — P3 PVDD182533_0 PVDD182533_0 PVDD182533_0 PVDD182533_0 Input controlling PVDD182533_0 power level with SW1-3 High: 3.3V, Low: 1.8V — — Y17 PVDD182533_1 PVDD182533_1 PVDD182533_1 PVDD182533_1 1.8V — — Y3 EXCLK EXCLK EXCLK EXCLK 24MHz input, connected to clock generator (IC31) for system clock — — P6 VDD18 VDD18 VDD18 VDD18 1.8V — — G6 MD_BOOT0 MD_BOOT0 MD_BOOT0 MD_BOOT0 Input BOOT_SEL0#, BOOT_SEL1# and BOOT_SEL2# logic states — — C5 MD_BOOT1 MD_BOOT1 MD_BOOT1 MD_BOOT1 Input BOOT_SEL0#, BOOT_SEL1# and BOOT_SEL2# logic states — — C4 MD_BOOT2 MD_BOOT2 MD_BOOT2 MD_BOOT2 Input BOOT_SEL0#, BOOT_SEL1# and BOOT_SEL2# logic states — — F20 MD_CLKS MD_CLKS MD_CLKS MD_CLKS Initial setting: 1 (Pull Up), should be controllable by resistor. — — A22 MD_OSCDRV0 MD_OSCDRV0 MD_OSCDRV0 MD_OSCDRV0 Initial setting: 0 (Pull Down), should be controllable by resistor. — — C21 MD_OSCDRV1 MD_OSCDRV1 MD_OSCDRV1 MD_OSCDRV1 Initial setting: 0 (Pull Down), should be controllable by resistor. — — AA2 NMI NMI NMI NMI Unused — — B2 OM_CS1# NC OM_CS1# P24_0 OctaRAM (IC3) Note: Unused in case of RZ/G2UL — — A4 OM_DQS NC OM_DQS P24_1 OctaFlash (IC2) and OctaRAM (IC3) Note: Unused in case of RZ/G2UL — — B4 OM_SIO4 NC OM_SIO4 P24_2 OctaFlash (IC2) and OctaRAM (IC3) Note: Unused in case of RZ/G2UL — — |
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