L9966 datasheet(27/122 Pages) STMICROELECTRONICS

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SEL[2:0] bits define if the current source is connected either to a pull up (and to which pull up voltage value

level among VPRE, 5V_REF and VVAR) or pull down source or high impedance. The choice of the connection

is defined through these 3 bits in conjunction with MODE bit that defines the “non-inversion / inversion” mode.

In case of IO[15:13], only PU-VPRE is possible and any PU to 5V_REF or VVAR is automatically redirected to

VPRE.

VVAR value is set through VAR_V[4:0] in DWT_VOLT_SRC_LSF_CTRL register. Every writing access to

DWT_VOLT_SRC_LSF_CTRL has impact on IOx configuration. For IO[12:9], the configuration is automatically

reset: in case LSF_MD_x=1, default configuration is 250 µA PU VDD5; in case LSF_MD_x=0, default

configuration is HiZ. IO[8:1] maintain their configuration and V(IOx) changes according to a new VVAR value

set.

MODE bit defines the non-inversion / inversion mode of the controlling input channel. MODE = 0 (Non Inv): the

configuration is done assigning to the control source a ‘1’ if the control source signal is high, a ‘0’ if the control

source signal is low. MODE = 1 (Inv): the configuration is done assigning to the control source a ‘0’ if the control

source signal is high, a ‘1’ if the control source is low.

In Table 16 the IOx setting based on SEL, MODE and the control signal is reported (see Figure 13): control signal

is considered as it is if MODE=0; it is considered its negated value if MODE=1

Table 16. IOx stage configuration

CURR_SRC_CTRL_x

SEL[2:0]

MODE = 0

MODE = 1

input signal

control signal

PU (VDD5, VPRE, VVAR)

PD or HiZ

input signal

control signal

PU (VDD5, VPRE, VVAR)

PD or HiZ

000

HiZ

001

Pu_VPRE

HiZ

010

Pu_5V_REF

HiZ

011

Pu_VVAR

HiZ

100

HiZ

101

Pu_VPRE

110

Pu_5V_REF

111

Pu_VVAR

000

HiZ

001

HiZ

Pu_VPRE

010

HiZ

Pu_5V_REF

011

HiZ

Pu_VVAR

100

HiZ

101

Pu_VPRE

110

Pu_5V_REF

111

Pu_VVAR

Figure 14 shows an example of configuration of CURR_SRC_CTRL_1 register in order to drive IO1 with 5 mA PU

to VPRE being MODE=1 and IO1 driven by IO3 which is here stuck at GND.

L9966

Control of current source

DS12459 - Rev 10

page 27/122

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