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Zakładka z wyszukiwarką danych komponentów |
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L9966 Arkusz danych(PDF) 35 Page - STMicroelectronics |
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L9966 Arkusz danych(HTML) 35 Page - STMicroelectronics |
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35 / 122 page  Symbol Parameter Condition Min Typ Max Unit Pin ADC1err_a_40 ADC1 total measurement error on analog inputs Including all error contributions (VDD5REF excl.) While no ratiometric comparator running Full range 40 V (1LSB = 10 mV) - - 90 LSB IO 1-12 ADC1err_d_1_25 ADC1 total measurement error on digital inputs Including all error contributions (VDD5REF excl.) While no ratiometric comparator running Full range 1.25 V (1LSB = 0.3 mV) - - 100 LSB IO 13-15 ADC1err_d_20 ADC1 total measurement error on digital inputs Including all error contributions (VDD5REF excl.) While no ratiometric comparator running Full range 20 V (1LSB = 5 mV) - - 100 LSB IO 13-15 ADC1err_d_40 ADC1 total measurement error on digital inputs Including all error contributions (VDD5REF excl.) While no ratiometric comparator running Full range 40 V (1LSB = 10 mV) - - 100 LSB IO 13-15 AFlexInputZ_1_25 Analog FlexInput input Impedance Full range: 1.25 V >>10M - - Ω IO 1-12 AFlexInputZ_5 Analog FlexInput input Impedance Full range: 5 V >>10M - - Ω IO 1-12 AFlexInputZ_20 Analog FlexInput input Impedance Full range: 20 V >200K - - Ω IO 1-12 AFlexInputZ_40 Analog FlexInput input Impedance Full range: 40 V >200K - - Ω IO 1-12 DflexInputZ_1_25 Digital FlexInput input Impedance Full range: 1.25 V >500K - - Ω IO 13-15 DflexInputZ_20 Digital FlexInput input Impedance Full range: 20 V >500K - - Ω IO 13-15 DflexInputZ_40 Digital FlexInput input Impedance Full range: 40 V >500K - - Ω IO 13-15 ADC1settl_1_25 ADC settling time Full range: 1.25 V Not to be programmed, already embedded in the logic -9% 4 +9% µs IO 1-15 ADC1settl_5 ADC settling time Full range: 5 V Not to be programmed, already embedded in the logic -9% 1.5 +9% µs IO 1-12 ADC1settl_20 ADC settling time Full range: 20 V Not to be programmed, already embedded in the logic -9% 15 +9% µs IO 1-15 ADC1settl_40 ADC settling time Full range: 40 V Not to be programmed, already embedded in the logic -9% 10 +9% µs IO 1-15 ADC1settl ADC settling time UBSW, VI5V, VIX, internal bandgap -9% 1.5 +9% µs - ADC1conv ADC conversion time Not considering ADCsettl -9% 40 +9% µs IO 1-15 L9966 ADC1: voltage measurement DS12459 - Rev 10 page 35/122 |
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