www.statschippac.com

FEATURES

• Body sizes: 4 x 4mm to 9 x 9mm

• Lead pitch: 0.50mm and 0.80mm

• Custom body / lead / pitch configurations available

• Package profile heights (overall): maximum 0.80mm

• Both single row & dual row design

• Ni / Pd / Au plated bumps

• Excellent thermal and electrical performance

• Full in-house package and leadframe design capability

• Full in-house electrical, thermal and mechanical

simulation and measurement capability

• JEDEC standard compliant

APPLICATIONS

•RF

• Power Management

• Analog/Linear

• Logic

• Applications requiring enhanced electrical and thermal

performance and reduced package size and weight

• Saw singulated format

• Package height 0.8mm max.

• Square body size (rectangular body designable)

• Staggered dual row or single row bump design

DESCRIPTION

STATS ChipPAC’s Bump Chip Carrier (BCC) technology pro-

duces a chip scale leadframe based molded package with

bumps which are formed after the leadframe is etched away.

An exposed die pad coupled with extremely low RLC provides

excellent electrical and thermal performance enhancements

which are ideal for high frequency and high power applica-

tions especially for handheld portable applications such as

cell phones. The BCC is manufactured in a molded array

format that maximizes product throughput and material

utilization. The BCC is available with single row and dual row

bumps in BCC++ and BCC+. Overall package profile height is

0.80mm maximum.

BCC

Bump Chip Carrier

BCC++ (exposed paddle with ground ring)

BCC+ (exposed paddle without ground ring)

BCCs++ (staggered dual row design)