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STM32L082KB Arkusz danych(PDF) 94 Page - STMicroelectronics |
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STM32L082KB Arkusz danych(HTML) 94 Page - STMicroelectronics |
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94 / 132 page  Electrical characteristics STM32L082xx 94/132 DS10688 Rev 7 Figure 26. Typical connection diagram using the ADC 1. Refer to Table 61: ADC characteristics for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 57: I/O static characteristics). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC must be reduced. 3. Refer to Table 57: I/O static characteristics for the value of Ilkg. 4. Refer to Figure 9: Power supply scheme. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 27 or Figure 28, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 27. Power supply and reference decoupling (VREF+ not connected to VDDA) MSv67871V3 Sample-and-hold ADC converter Converter Cparasitic (2) Ilkg (3) CADC VDDA (4) RAIN (1) VAIN RADC VREF+ (4) VSSA I/O analog switch Sampling switch with multiplexing VSS VSS MS39601V1 VREF+ STM32Lxx VDDA VSSA / VREF– 1 μF // 100 nF 1 μF // 100 nF |
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