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STM32L082KB Arkusz danych(PDF) 105 Page - STMicroelectronics |
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STM32L082KB Arkusz danych(HTML) 105 Page - STMicroelectronics |
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105 / 132 page ![]() DS10688 Rev 7 105/132 STM32L082xx Electrical characteristics 109 Table 73. SPI characteristics in voltage Range 3 (1) Symbol Parameter Conditions Min Typ Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode -- 2 MHz Slave mode 2(2) Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - ns th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 tsu(MI) Data input setup time Master mode 1.5 - - tsu(SI) Slave mode 6 - - th(MI) Data input hold time Master mode 13.5 - - th(SI) Slave mode 16 - - ta(SO Data output access time Slave mode 30 - 70 tdis(SO) Data output disable time Slave mode 40 - 80 tv(SO) Data output valid time Slave mode - 30 70 tv(MO) Master mode - 7 9 th(SO) Data output hold time Slave mode 25 - - th(MO) Master mode 8 - - 1. Guaranteed by characterization results. 2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. |
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