IS43R16800A1 datasheet(4/72 Pages) ISSI

4 / 72 page

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

04/17/06

ISSI®

IS43R16800A1

PIN FUNCTIONS

Symbol

Type

Function (In Detail)

A0-A11

Input Pin

Address inputs are sampled during several commands. During an Active

command, A0-A11 select a row to open. During a Read or Write command,

A0-A8 select a starting column for a burst. During a Pre-charge command,

A10 determines whether all banks are to be pre-charged, or a single bank.

During a Load Mode Register command, the address inputs select an

operating mode.

BA0, BA1

Input Pin

Bank Address inputs are used to select a bank during Active, Pre-charge,

Read, or Write commands. During a Load Mode Register command, BA0

and BA1 are used to select between the Base or Extended Mode Register

CAS

Input Pin

CAS is Column Access Strobe, which is an input to the device command

along with

RAS and WE. See “Command Truth Table” for details.

CKE

Input Pin

Clock Enable: CKE High activates and CKE Low de-activates internal clock

signals and input/output buffers. When CKE goes Low, it can allow Self

Refresh, Pre-charge Power Down, and Active Power Down. CKE must be

High during entire Read and Write accesses. Input buffers except CK,

CK, and CKE are disabled during Power Down. CKE uses an SSTL 2

input, but will detect a LVCMOS Low level after VDD is applied.

CK,

Input Pin

All address and command inputs are sampled on the rising edge of the

clock input CK and the falling edge of the differential clock input

CK.

Output data is referenced from the crossings of CK and

CK.

Input Pin

The Chip Select input enables the Command Decoding block of the device.

When

CS is disabled, a NOP occurs. See “Command Truth Table” for

details. Multiple DDR SDRAM devices can be managed with

CS.

LDM, UDM

Input Pin

These are the Data Mask inputs. During a Write operation, the Data Mask

input allows masking of the data bus. DM is sampled on each edge of DQS.

There are two Data Mask input pins for the x16 DDR SDRAM. Each input

applies to DQ0-DQ7, or DQ8-DQ15.

LDQS, UDQS

Input/Output Pin

These are the Data Strobe inputs. The Data Strobe is used for data capture.

During a Read operation, the DQS output signal from the device is edge-

aligned with valid data on the data bus. During a Write operation, the DQS

input should be issued to the DDR SDRAM device when the input values on

DQ inputs are stable. There are two Data Strobe pins for the x16 DDR

SDRAM. Each of the two Data Strobe pins applies to DQ0-DQ7, or DQ8-

DQ15.

DQ0-DQ15

Input/Output Pin

The pins DQ0 to DQ15 represent the data bus. For Write operations, the

data bus is sampled on Data Strobe. For Read operations, the data bus is

sampled on the crossings of CK and

CK.

—

No Connect: This pin should be left floating. These pins could be used for

256Mbit or higher density DDR SDRAM.

RAS

Input Pin

RAS is Row Access Strobe, which is an input to the device command

along with

CAS and WE. See “Command Truth Table” for details.

Input Pin

WE is Write Enable, which is an input to the device command along with

RAS and CAS. See “Command Truth Table” for details.

VDDQ

Power Supply Pin

VDDQ is the output buffer power supply.

VDD

Power Supply Pin

VDD is the device power supply.

VREF

Power Supply Pin

VREF is the reference voltage for SSTL 2.

VSSQ

Power Supply Pin

VSSQ is the output buffer ground.

VSS

Power Supply Pin

VSS is the device ground.

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