HC05V7GRSSLASHD datasheet(16/170 Pages) NXP

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SECTION 1: GENERAL DESCRIPTION

Page 2

MC68HC05V7 Specification Rev. 1.0

NOTE:

A line over a signal name indicates an active low signal. For example,

RESET is active high and RESET is active low. Any reference to voltage,

current, or frequency specified in the following sections will refer to the

nominal values. The exact values and their tolerance or limits are

specified in SECTION 17 ELECTRICAL SPECIFICATIONS.

1.2

MASK OPTIONS

The following mask options are available:

•

Sensitivity on IRQ Interrupt, Edge- and Level-Sensitive or Edge-Sensitive

Only

•

Selectable COP Watchdog System

•

Selectable Low Voltage Reset (LVR)

•

Selectable STOP Instruction Disable

•

Selectable on-chip power supply regulator

•

Selectable option to allow regulator wakeup on a rising edge of the MDLC

Bus

•

Selectable option to tie the regulator output to VSS when turned off

1.3

PIN ASSIGNMENTS

The MC68HC05V7 requires 64 bond pads for all I/O and power supply functions. The

device is available in a 56-pin SDIP package where the 8 A/D channels associated with

Port E are not bonded out (AN8 thru AN15). The device is also available in the 68 pin PLCC

and 64 pin QFP packages.

The pin out for the 56-pin SDIP, the 68-pin PLCC, and the 64-pin QFP packages are shown

in the following figures. The pad positions are also in the following figures.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Arkusz danych(PDF) 16 Page - NXP Semiconductors