HC05V7GRSSLASHD datasheet(101/170 Pages) NXP

101 / 170 page

SECTION 14: SERIAL PERIPHERAL INTERFACE

Page 87

MC68HC05V7 Specification Rev. 1.0

Figure 14-3:

Serial Peripheral Interface Master-Slave Interconnection

14.3

SPI REGISTERS

There are three registers in the SPI which provide control, status, and data storage

functions. These registers are called the serial control register (SPCR), serial peripheral

status register (SPSR), and serial peripheral data I/O register (SPDR) and are described in

the following paragraphs.

14.3.1

Serial Peripheral Control Register (SPCR)

Figure 14-4:

SPI Control Register (SPCR)

SPIE - Serial Peripheral Interrupt Enable

0 = SPIF interrupts disabled

1 = SPI interrupt is SPIF=1

SPE - Serial Peripheral System Enable

0 = SPI system off

1 = SPI system on. Port F becomes SPI pins. SS is a special case. See 9.4

PORT F for additional information.

MSTR - Master Mode Select

0 = Slave mode

1 = Master mode

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

MOSI

SPI CLOCK

GENERATOR

SCK

SLAVE

MASTER

VDD

SPIE

—

MSTR

CPOL

CPHA

SPR1

SPR0

SPE

$0A

0001

RESET:

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Arkusz danych(PDF) 101 Page - NXP Semiconductors

HC05V7GRS/D Arkusz danych(HTML) 101 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL