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ADC1283 Arkusz danych(PDF) 5 Page - STMicroelectronics |
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ADC1283 Arkusz danych(HTML) 5 Page - STMicroelectronics |
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5 / 24 page ![]() Symbol Parameters Test conditions Min. Typ. Max. Unit IM3 3rd order intermodulation FIN = 19.5 / 20.5 kHz, -0.02 dBFS AVCC = DVCC = 3.3 V -87 dB FIN = 19.5 / 20.5 kHz, -0.02 dBFS AVCC =ˆDVCC = 5 V -88 Analog input characteristics (AVCC = 2.7 V to 5.5 V) IDCL DC leakage current -1 0.01 +1 µA CINA Input capacitance Track mode 33 pF Hold mode 4.5 pF Digital input characteristics VIH Input high voltage DVCC = 2.7 V to 5.5 V 0.7xDVCC V VIL Input low voltage DVCC = 2.7 V to 5.5 V 0.3xDVCC VOH (1) Output high voltage DVCC = 3.3 V, Isource = -1 mA DVCC-0.5 V V DVCC = 5 V, Isource = -1 mA DVCC-0.5 V VOL (1) Output low voltage DVCC = 3.3 V, Isink = 1 mA 0.4 DVCC = 5 V, Isink = 1 mA 0.4 IIN Digital input current VIN = 0 V or DVCC -1 0.01 1 µA CIND Digital input capacitance DVCC = 2.7 V to 5.5 V 3.5 pF IOZH, IOZL Hi-impedance output leakage current -1 0.02 1 µA COUT Hi-impedance output capacitance 3.5 pF Power supply characteristic IAVCC + IDVCC Total supply current, normal mode (CS low) AVCC = DVCC = 2.7 V to 5.5 V, fS = 200 kSPS, FIN = 40 kHz 0.64 0.8 mA Total supply current, shutdown mode (CS high) AVCC = DVCC = 2.7 V to 5.5 V, fS = 0, -40 °C < T < 85 °C 0.02 2 µA AVCC = DVCC = 2.7 V to 5.5 V, fS = 0, 85 °C < T < 125 °C 10 AC characteristics (AVCC = DVCC = 2.7 V to 5.5 V) fS Sample rate 50 200 ksps tCONVERT Conversion (Hold) time 13 SCLK cycles DC SCLK duty cycle 40 60 % tACQ Acquisition (Track) time cycles See Figure 4 3 SCLK cycles Throughput time Acquisition time + Conversion time 16 SCLK cycles tAD Aperture delay 4 ns Timing specifications (AVCC = 2.7 V to 5.5 V) (1)(2) tCSH CS hold time after SCLK rising edge 10 0 ns tCSS CS set-up time prior SCLK rising edge 10 4.5 ns tEN CS falling edge to DOUT enabled 6 30 ns ADC1283 Electrical characteristics DS13932 - Rev 1 page 5/24 |
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