7

Application information

7.1

Functional description of the ADC1283

The ADC1283 implements a successive-approximation-register (SAR) structure to perform the conversion of

analog signals into 12-bit pure binary digital outputs. As shown in the block diagram in Figure 37, it is made

of capacitive Track and Hold, SAR ADC and control logic. The conversion circuit includes a fast settling time

comparator to convey instruction into the register to store digital 0 or 1, and a redistribution DAC with logic control

to have the ADC compare the track signal with a reference signal at each clock cycle.

The conversion is carried out in two phases. The sampling phase conveys the input signal through the

capacitance array for the first 3 clock-cycles and the evaluation phase performs the conversion into digital 12-bit

signal within 13 clock cycles. At each clock cycle of the evaluation phase, the hold signal is compared with a

new value distributed by the DAC and the result is stored in the 12-bit register, MSB first. 13 clock cycles are

necessary for this second step. So, a full conversion requires 16 clock cycles to generate a new 12-bit word on

the DOUT pin.

Figure 37. Functional block diagram

7.2

Analog inputs

The inputs are single-ended and referenced from AVCC to AGND, since AVCC behaves as internal reference

(refer to Table 1. Pin description). The dynamic range is AVCC and the LSB (Least Significant Bit) is:

LSB=AVCC212

(1)

The capacitance seen on the input varies depending on conversion step. During the sampling phase, a 33 pF is

seen from the input, thus care must be taken to the front-end driver to support this load.

The schematic below shows the equivalent input circuit.

Figure 38. Equivalent input circuit

To avoid aliasing of the input signals toward unwanted frequencies, it is recommended to insert a low-pass filter

whose value is fixed depending on inputs frequency and sampling rate.

ADC1283

Application information

DS13932 - Rev 1

page 15/24