ADE7762 datasheet(18/28 Pages) AD

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ADE7762

Preliminary Technical Data

Rev. PrB | Page 18 of 28

POWER SUPPLY MONITOR

The ADE7762 contains an on-chip power supply monitor. The

power supply (VDD) is monitored continuously by the ADE7762.

At power up, when the supply is less than 4V ±2% and VREF is less

than 1.9 V (typ), the outputs of the ADE7762 are inactive and the

data path is held in reset. Once VDD is greater than 4V ±2% and

VREF is greater than 1.9 V (typ), the chip is active and energy

accumulation begins. At power-down, when VDD falls below 4 V

or VREF falls below 1.9 V (typ), the data path is again held in reset.

This implementation ensures correct device operation at power-

up and at power-down. The power supply monitor has built-in

hysteresis and filtering. This gives a high degree of immunity to

false triggering due to noisy supplies.

The power supply and decoupling for the part should be such

that the ripple at VDD does not exceed ±5% as specified for

normal operation.

VDD

VREF

INTERNAL

RESET

ACTIVE

INACTIVE

2.4V

1.9V

INACTIVE

Figure 24. On-Chip Power Supply Monitor

ADE7762 Arkusz danych(PDF) 18 Page - Analog Devices