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AM79C874VC Arkusz danych(PDF) 50 Page - Advanced Micro Devices |
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AM79C874VC Arkusz danych(HTML) 50 Page - Advanced Micro Devices |
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50 / 60 page ![]() 50 Am79C874 P R E L I M INARY 100 Mbps MII Receive Timing Figure 20. 100 Mbps MII Receive Start of Packet Timing Symbol Parameter Description Min. Max. Unit tMRJCRH100 CRS HIGH After First Bit of /J/ - 200 ns tMRJCOH100 COL HIGH After First Bit of /J/ 80 150 ns tMRTCRL100 First Bit of /T/ to CRS LOW 130 240 ns tMRTCOL100 First Bit of /T/ to COL LOW 130 240 ns tMRERL100 First Bit of /T/ to RXD[3:0], RX_DV De-Asserting (Going LOW) 120 140 ns tMRJRA100 First Bit of/J/ to RXD[3:0], RX_DV, and RX_EN Active TBD TBD ns tMRRDC100 RXD[3:0], RX_DV, RX_ER valid prior to the Rising Edge of RX_CLK 10 ns tMRCRD100 RXD[3:0], RX_DV, RX_ER valid after the Rising Edge of RX_CLK 10 ns RX± CRS COL RX_DV tMRJCOH100 tMRJRA100 /J/K/ RX_CLK RXD[3:0] RX_ER tMRJCRH100 tMRRDC100 tMRCRD100 22235I-22 |
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