AM79C874VC datasheet(11/60 Pages) AMD

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Am79C874

P R E L I M INARY

TX_ER/TXD[4]

Transmit Error

Input

When TX_ER is asserted, it will cause the 4B/5B en-

coding process to substitute the transmit error code-

group /H/ for the encoded data word.

This pin becomes the higher-order bit of the transmit 5-

bit code group in PCS bypass (PCSBP=HIGH) mode.

This input is ignored in the 10BASE-T operation.

TX_CLK/10TXCLK/PCSBPCLK

Transmit Clock

Output, High Impedance

A free-running clock which provides timing reference

for TX_EN, TX_ER, and TXD[3:0] signals. It is 25 MHz

in 100BASE-TX/FX and 2.5 MHz in 10BASE-T.

When 7-wire GPSI mode is enabled, this pin will pro-

vide a 10 MHz transmit clock for 10BASE-T operation.

When the cable is unplugged, the 10TXCLK ceases

operation.

When working in PCSBP mode, this pin will provide a

25 MHz clock for 100BASE-TX operation, and 20 MHZ

clock for 10BASE-T operation. TX_CLK is high imped-

ance when the ISO pin is enabled.

TX_EN/10TXEN

Transmit Enable

Input

The TX_EN pin is asserted by the MAC to indicate that

data is present on TXD[3:0].

When 7-wire 10BASE-T mode is enabled, this pin is the

transmit enable signal.

TXD[3:1]

Transmit Data

Input

The MAC will source TXD[3:1] to the PHY. The data will

be synchronous with TX_CLK when TX_EN is as-

serted. The PHY will clock in the data based on the ris-

ing edge of TX_CLK.

TXD[0]/10TXD

Transmit Data[0]/10 Mbps Transmit Data

Input

The MAC will source TXD[0] to the PHY. The data will

be synchronous with TX_CLK when TX_EN is as-

serted. The PHY will clock in the data based on the ris-

ing edge TX_CLK.

When 7-wire 10BASE-T mode is enabled, this pin will

transmit serial data.

COL/10COL

Collision

Output, High Impedance

COL is asserted high when a collision is detected on

the media. COL is also used for the SQE test function

in 10BASE-T mode.

10COL is asserted high when a collision is detected

during 7-wire interface mode.

CRS/10CRS

Carrier Sense

Output, High Impedance

CRS is asserted high when twisted pair media is non-

idle. This signal is used for both 10BASE-T and

100BASE-X. In full duplex mode, CRS responds only to

RX activity. In half duplex mode, CRS responds to both

RX and TX activity.

10CRS is used as the carrier sense output for the

7-wire interface mode.

Miscellaneous Functions

PCSBP

PCS Bypass

Input, Pull-Down

The 100BASE-TX PCS as well as scrambler/descram-

bler will be bypassed when PCSBP is pulled high via a

10 k

W resistor. TX_ER will become TXD[4] and RX_ER

will become RXD[4].

In 10 Mbps PCS bypass mode, the MII signals are not

valid. The signals that interface to the MAC (i.e.,

DECPC 21143) are located on pins 14 to 19. The sig-

nals are defined as follows:

— 10RXD± are the differential receive outputs to

the MAC.

— 10TXD± are the differential transmit inputs from

the MAC.

— 10TXD++/10TXD-- are the differential pre-

emphasis transmit outputs from the MAC.

When left unconnected, the device operates in MII or

GPSI mode.

ISODEF

Isolate Default

Input, Pull-Down

This pin is used when multiple PHYs are connected to

a single MAC. When it is pulled high via a 10 k

W resis-

tor, the MII interface will be high impedance. The status

of this pin will be latched into MII Register 0, bit 10 after

reset.

When this pin is left unconnected, the default condition

of the MII output pins are not in the high impedance

state.

ISO

Isolate

Input, Pull-Down

The MII output pins will become high impedance when

ISO is pulled high via a 10 k

W resistor. However, the MII

input pins will still respond to data. This allows multiple

PHYs to be attached to the same MII interface. The

same isolate condition can also be achieved by assert-

ing MII Register 0, bit 10. In repeater mode, ISO will not

tri-state the CRS pin.

When this pin is left unconnected, the MII output pins

are not in the high impedance state.

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