ADP1822

Rev. B | Page 8 of 24

Pin

No.

Mnemonic

Description

17

MDN

Margin Down Input. Connect a resistor from MDN to the output voltage to set the low margining voltage.

See the Setting the Voltage Margin section.

18

MUP

Margin Up Input. Connect a resistor from MUP to GND to set the high margining voltage.

See the Setting the Voltage Margin section.

19

VCC

Internal Power Supply Input. VCC powers the internal circuitry. Bypass VCC to GND with 0.1 μF or greater capacitor

connected as close as possible to the IC.

20

CSL

Low-Side Current Sense Input. Connect CSL to SW through a resistor to set the current limit.

See the Setting the Current Limit section.

21

PGND

Power Ground. Connect GND to PGND at a single point as close as possible to the IC.

22

DL

Low-Side Gate Driver Output. Connect DL to the gate of the low-side N-channel MOSFET synchronous rectifier.

The DL voltage swings between PGND and PVCC.

23

PVCC

Internal Gate Driver Power Supply Input. PVCC powers the low-side gate driver DL. Bypass PVCC to PGND with 1 μF or

greater capacitor connected as close as possible to the IC.

24

NC

No Connection. Not internally connected.