4

DS700DB1

CDB53L21

1. SYSTEM OVERVIEW

The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Digital audio signal out-

puts are provided, and an FPGA is used for easily configuring the board. Section 2. “Software Mode Control” on

page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

The CDB53L21 schematic set has been partitioned into seven pages and is shown in Figures 27 through 33. “Sys-

tem Connections and Jumpers” on page 20 provides a description of all stake headers and connectors, including

the default factory settings for all jumpers.

1.1

Power

Power is supplied to the evaluation board through the +5.0 V binding posts. Jumpers connect the ADC’s

supplies to a regulated voltage of +1.8 V, 2.5 V or +3.3 V for VL and +1.8 V or 2.5 V for VD and VA. All volt-

age inputs must be referenced to the black binding post ground connector.

For current measurement purposes only, a series resistor is connected to each supply. The current is easily

calculated by measuring the voltage drop across this resistor. NOTE: The stake headers connected in par-

allel with these resistors must be shunted with the supplied jumper during normal operation.

WARNING: Please refer to the CS53L21 data sheet for allowable voltage levels.

1.2

Grounding and Power Supply Decoupling

The CS53L21 requires careful attention to power supply and grounding arrangements to optimize perfor-

mance. The CDB53L21 demonstrates these optimal arrangements. Figure 26 on page 22 provides an over-

view of the connections to the CS53L21. Figure 34 on page 30 shows the component placement, Figure 35

on page 31 shows the top layout, and Figure 36 on page 32 shows the bottom layout. The decoupling ca-

pacitors are located as close to the CS53L21 as possible. Extensive use of ground plane fill in the evaluation

board yields large reductions in radiated noise.

1.3

FPGA

The FPGA provides digital signal routing between the CS53L21, CS8406 and the I/O stake header. It also

configures the Hardware Mode options of the CS8406 and provides routing control of the system master

clock from an on-board oscillator and the I/O stake header. The Cirrus FlexGUI software and “FPGA H/W

Control” switches provide full control of the FPGA’s routing and configuration options. Section 2. “Software

Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

1.4

CS53L21 Audio A to D Converter

A complete description of the CS53L21 (Figure 27 on page 23) is included in the CS53L21 product data

sheet.

The CS53L21 may be configured using either the Cirrus FlexGUI or the on-board “CS53L21 H/W Control”

switches. The Software Mode control port registers are accessible through the “Register Maps” tab of the

Cirrus FlexGUI software. This tab provides low-level control of each bit. For easier configuration, additional

tabs provide high-level control. The Hardware Mode, stand-alone controls for the CS53L21 are accessible

through the on-board, stand-alone switches, “CS53L21 H/W Control.”

Clock and data source selections are made in the control port of the FPGA, accessible through the “General

Configurations” tab of the Cirrus FlexGUI software or through the on-board “FPGA H/W Control” switches.

Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide

configuration details.