STE100A datasheet(46/82 Pages) STMICROELECTRONICS

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Registers and descriptors description

STE10/100A

46/82

CSR7 (offset = 38h), IER - Interrupt enable register

31~17

---

Reserved

NIE

Normal interrupt enable.

1: enables all the normal interrupt bits (see bit 16

of CSR5).

0R/W

AIE

Abnormal interrupt enable.

1: enables all the abnormal interrupt bits (see bit

15 of CSR5).

0R/W

---

Reserved

FBEIE

Fatal bus error interrupt enable.

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the fatal bus error interrupt.

0R/W

---

Reserved

GPTIE

General purpose timer interrupt enable.

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the general purpose timer

expired interrupt.

0R/W

---

Reserved

9RWTIE

Receive watchdog time-out interrupt enable

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the receive watchdog time-out

interrupt.

0R/W

8RSIE

Receive stopped interrupt enable.

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the receive stopped interrupt.

0R/W

7RUIE

Receive descriptor unavailable interrupt enable.

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the receive descriptor

unavailable interrupt.

0R/W

RCIE

Receive completed interrupt enable.

1: this bit in conjunction with NIE (bit 16 of

CSR7) will enable the receive completed

interrupt.

0R/W

5TUIE

Transmit under-flow interrupt enable.

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the transmit under-flow

interrupt.

0R/W

---

Reserved

TJTTIE

Transmit jabber timer time-out interrupt enable.

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the transmit jabber timer time-

out interrupt.

0R/W

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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