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MAS9560 Arkusz danych(PDF) 18 Page - Micro Analog systems

Numer części MAS9560
Szczegółowy opis  Stereo Audio Driver DAC
PDF  25 Pages
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Producent  MAS [Micro Analog systems]
Strona internetowa  http://www.mas-oy.com
Logo MAS - Micro Analog systems

MAS9560 Arkusz danych(HTML) 18 Page - Micro Analog systems

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DA9560.001
20 January, 2005
Figure 1. I
2S Bus
◆ Resetting Registers
When I
2C is used:
First register 0x00 is the reset register, writing to
which will set all registers to default values. Writing
to register 0x00 sets default values to all registers,
after which following data will be written to registers
as incrementing starts. However, note that when
starting data write with the reset sequence, the byte
following the reset address is unused and the byte
after that is written to register 0x01 (DW-byte,
Reset-address-byte, unused data byte, data byte
for register 0x01). On-chip incremental counter is 4-
bits long: at address 0x0F incrementing stops.
When SPI is used:
Writing to the first register (0x00) resets all
registers. In case writing sequence is started with
reset, the byte following the reset address is
unused, similarly to I
2C-mode.
Register reset can be performed externally by
setting XRESET pin low.
CONTROL REGISTERS
MAS9560 has 11 on-chip registers, which are
controlled through I
2C- or SPI-bus (see section
Control Interfaces above). Register byte length is 8
bits for all registers, however, some bits are unused
and their value is not set and can vary (they are
non-repeatable). Reset register is write-only, all
other registers permit read and write access.
◆ Register Map
Sub-Address
Register
0x00
Reset Register
0x01
Block Control Register
0x02
Mode Control Register
0x03
I
2S-Interface Control Register
0x04
Left Headphone Volume Control
0x05
Right Headphone Volume Control
0x06
Earpiece Volume Control
0x07
Loudspeaker Volume Control
0x08
Left Input Aux Gain Control
0x09
Right Input Aux Gain Control
0x0A
Ain Input Gain Control
0x0B… 0x0F
Unused
CLI
DAI
WSI
left 16-bit audio sample
right 16-bit audio sample
programmable delay bit
V
h -
V
l -
V
h -
V
l -
V
h -
V
l -



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