ES9822PRO datasheet(50/126 Pages) ESS

50 / 126 page

0.3

ES9822 PRO Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

Bits

[7:6]

[5]

[4]

[3]

[2:0]

Default

2'd0

1'b0

3'd0

Bits

Mnemonic

Description

[7:6]

OUTPUT2_SEL

Selects DATA2 output (GPIO4) when "FORCE_OUTPUT2" is

set.

•

2'd0 -> I2S (default)

•

2'd1 -> SPDIF

•

2'd2 -> TDM

•

2'd3 -> DSD

[5]

FORCE_OUTPUT2

Forces DATA2 output (GPIO4) to output from a different

source, controlled by "OUTPUT2_SEL".

•

1'b0: Use "OUTPUT_SEL" (default)

•

1'b1: Use "OUTPUT2_SEL"

[4]

INVERT_FIRST_CLK_SAMPLE2

Firstly, use neg edge of CLK_SAMPLE2 to sample

adc_data_r1.

Only used when different CLK_SAMPLE1 edges are used for

the 2ch to ensure phase alignment.

•

1'b0: Use pos edge of CLK_SAMPLE2 to sample

adc_data_r1 (default)

•

1'b1: Use neg edge of CLK_SAMPLE2 to sample

adc_data_r1

[3]

SELECT_IADC_HALF

•

1'b0: Divide by SELECT_IADC_NUM + 1 (default)

•

1'b1: Divide by half of SELECT_IADC_NUM + 1

Note: Can only produce half of an odd number divide

[2:0]

SELECT_IADC_NUM

Whole number divide value + 1 for CLK_IADC

(SYS_CLK/divide_value).

•

3'd0: Whole number divide value + 1 = 1 (default)

•

3'd1: Whole number divide value + 1 = 2

•

3'd7: Whole number divide value + 1 = 8

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