ES9822PRO datasheet(121/126 Pages) ESS

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ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

121

ES9822 PRO Product Datasheet

TDM Master

FS=48kHz, 2 Channel, MCLK=49.152MHz

w 0x48 193 0x01; //SEL_SYSCLK_IN = 00 (XTAL), EN_ANA_CLKIN = 1

//w 0x48 193 0x05; //SEL_SYSCLK_IN = 10 (ACLK), EN_ANA_CLKIN = 1

w 0x48 194 0x01; //SEL_CLK_DIV = 1/2 (for 49.152/45.1584MHz, this sets ADC clock rate, must be 22

or 24MHz)

w 0 0x40;

//OUTPUT_SEL = 10 (TDM)

w 1 0x33;

//ENABLE_ADC_CH and ENABLE_DATA_IN_CH

w 2 0x07;

//SELECT_ADC_NUM = 7 for 48k/44.1k, 3 for 96k, 1 for 192k

w 3 0x01;

//SELECT_IADC_NUM = 1, should match SEL_CLK_DIV

w 8 0x07;

//MASTER_BCK_DIV1 = 0, MASTER_MODE_ENABLE = 1

w 9 0x07;

//SELECT_I2S_TDM_NUM = 7 for 48k/44.1k, 3 for 96k, 1 for 192k (must match Reg 2)

w 10 0x03;

//TDMLJ format: TDM_LJ = 1, TDM_VALID_EDGE = 0, ENABLE_TDM_CLK = 1

//w 10 0x05;

//TDMI2S format: TDM_LJ = 0, TDM_VALID_EDGE = 1, ENABLE_TDM_CLK = 1

w 11 0x01;

//TDM_CH_NUM = 1 (# of channels = 1 + TDM_CH_NUM)

w 12 0x00;

//TDM_LINE_SEL_CH1: 00 (GPIO3),

TDM_SLOT_SEL_CH1: 0 (slot 0)

w 13 0x01;

//TDM_LINE_SEL_CH2: 00 (GPIO3),

TDM_SLOT_SEL_CH2: 1 (slot 1)

w 23 0x0A;

//FS_PHASE = 10

w 33 0x95;

//TDMLJ format: SYNC_POSEDGE_FRAME = 1

//w 33 0x15;

//TDMI2S format: SYNC_POSEDGE_FRAME = 0

//GPIO enabling

w 74 0x22;

//GPIO1_CFG and GPIO2_CFG set to AUX output (clocks out)

w 75 0x02;

//GPIO3_CFG set to AUX output (data out)

w 86 0x03;

//GPIO1_SDB and GPIO2_SDB input enabled

w 88 0x07;

//GPIO1_OE and GPIO2_OE and GPIO3_OE output enabled

//ADC CONFIG

w 63 0xBB; //adc ch1a config

w 64 0x38;

w 65 0xBB; //adc ch2a config

w 66 0x38;

w 67 0xBB; //adc ch1b config

w 68 0x38;

w 69 0xBB; //adc ch2b config

w 70 0x38;

w 71 0xFF; //set common mode to 3

//ADC filter and datapath registers

w 113 0x98; //ADC1A_FILTER_SHAPE = Minimum phase slow roll off

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