Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

WM8766 Arkusz danych(PDF) 16 Page - Wolfson Microelectronics plc

Numer części WM8766
Szczegółowy opis  24-bit, 192kHz 6-Channel DAC
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  WOLFSON [Wolfson Microelectronics plc]
Strona internetowa  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8766 Arkusz danych(HTML) 16 Page - Wolfson Microelectronics plc

Back Button WM8766 Datasheet HTML 12Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 13Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 14Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 15Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 16Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 17Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 18Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 19Page - Wolfson Microelectronics plc WM8766 Datasheet HTML 20Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 36 page
background image
WM8766
Production Data
w
PD Rev 4.1 July 2005
16
AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters via the Digital Audio Interface. 5 popular interface
formats are supported:
Left Justified mode
Right Justified mode
I2S mode
DSP mode A
DSP mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
In left justified, right justified and I
2S modes, the digital audio interface receives DAC data on the
DIN1/2/3 inputs. Audio data for each stereo channel is time multiplexed with LRCLK indicating
whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the
beginning or end of the data words.
In left justified, right justified and I
2S modes, the minimum number of BCLKs per LRCLK period is 2
times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low
for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the
above requirements are met.
In DSP modes A or B, all 6 DAC channels are time multiplexed onto DIN1. LRCLK is used as a
frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK
period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided
the rising edge is correctly positioned.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8766 on the first rising edge of
BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right
samples, see Figure 13.
Figure 13 Left Justified Mode Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Arkusz danych Pobierz

Go To PDF Page


Link URL



Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Link do karty katalogowej    |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com