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Production Data

WM8766

PD Rev 4.1 July 2005

SOFTWARE CONTROL INTERFACE OPERATION

The WM8766 is controlled using a 3-wire serial interface in software mode or pin programmable in

hardware mode.

The control mode is selected by the state of the MODE pin.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is

used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire

interface protocol is shown in Figure 18.

B15

B14

B13

B12

B11

B10

ML/I2S

MC/IWL

MD/DM

Figure 18 3-wire SPI Compatible Interface

B[15:9] are Control Address Bits

B[8:0] are Control Data Bits

ML/I2S is edge sensitive – the data is latched on the rising edge of ML/I2S.

CONTROL INTERFACE REGISTERS

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and

right channel DACs from the next audio input sample. No update to the attenuation registers is

required for ATC to take effect.

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

DAC Channel Control

ATC

Attenuator Control Mode:

0: Right channels use right

attenuations

1: Right channels use left

attenuations

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