AM29BDS640G datasheet(53/77 Pages) AMD

53 / 77 page

May 9, 2006 25903C2

Am29BDS640G

Data

Sheet

AC Characteristics

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

3. The device is in synchronous mode.

4. In the Burst Mode Configuration Register, A17 = 1.

Figure 13. Synchronous Burst Mode Read

Note: Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in

data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap

around within the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting

address in figure is the 7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The

Set Configuration Register command sequence has been written with A18=1; device will output RDY with valid data.

Figure 14. 8-word Linear Burst with Wrap Around

Da + 1

Da + n

OE#

DQ15-DQ0

A21-A0

AVD#

RDY

CLK

CE#

tCAS

tAAS

tAVC

tAVD

tAAH

tOE

tRACC

tOEZ

tCEZ

tIACC

tBDH

7 cycles for initial access shown.

Hi-Z

tRDYS

tBACC

tACC

OE#

DQ15-DQ0

A21-A0

AVD#

RDY

CLK

CE#

tCES

tACS

tAVDS

tAVD

tACH

tOE

tIACC

tBDH

7 cycles for initial access shown.

18.5 ns typ. (54 MHz)

Hi-Z

tRACC

456

tRDYS

tBACC

tACC

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