CS8416-CSZ datasheet(14/60 Pages) CIRRUS

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DS578F3

CS8416

2.2

QFN Pin Description

Name

Pin #

Pin Description

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise

as possible since noise on this pin will directly affect the jitter performance of the recovered clock

Digital Power (Input) – Digital core power supply. Nominally +3.3 V

Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

AGND

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-

nected to a common ground area under the chip.

DGND

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected

to a common ground area under the chip.

RST

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.

On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable

in frequency and phase.

FILT

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on

page 53 for more information on the PLL and the external components.

Top-Down View

28-pin QFN Package

Thermal Pad

RXP0

RXN

AGND

FILT

RST

RXP4

RMCK

DGND

GPO0

GPO1

AD2 / GPO2

CS8416-CSZ Arkusz danych(PDF) 14 Page - Cirrus Logic