PM7367 datasheet(100/323 Pages) PMC

100 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

Bit

Type

Function

Default

Bit 31

Bit 16

Unused

XXXXH

Bit 15

TFUDRI

Bit 14

IOCI

Bit 13

TDFQEI

Bit 12

TDQRDYI

Bit 11

TDQFI

Bit 10

RPDRQEI

Bit 9

RPDFQEI

Bit 8

RPQRDYI

Bit 7

RPQLFI

Bit 6

RPQSFI

Bit 5

RFOVRI

Bit 4

RPFEI

Bit 3

RABRTI

Bit 2

RFCSEI

Bit 1

PERRI

Bit 0

SERRI

This register reports the interrupt status for various events detected or initiated

by the FREEDM. Reading this registers acknowledges and clears the interrupts.

Note

This register is not byte addressable. Reading this register clears all the interrupt

bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not

implemented. However, when all four byte enables are negated, no access is

made to this register.

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