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PPC405EP Arkusz danych(PDF) 45 Page - Applied Micro Circuits Corporation

Numer części PPC405EP
Szczegółowy opis  PowerPC 405EP Embedded Processor
PDF  50 Pages
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Producent  AMCC [Applied Micro Circuits Corporation]
Strona internetowa  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

PPC405EP Arkusz danych(HTML) 45 Page - Applied Micro Circuits Corporation

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PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
AMCC
45
Data Sheet
Table 14. I/O Specifications—Group 1 (Sheet 1 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.
3. For PCI, IOH is specified at 0.9OVDD and IOL is specified at 0.1OVDD. For all other interfaces, IOH is specified at 2.4V and IOL
is specified at 0.4V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
IOH
(min)
IOL
(min)
PCI Interface
PCIAD31:00
3
0
6
1
0.5
1.5
PCIClk
1
PCIC3:0/BE3:0
30
6
1
0.5
1.5
PCIClk
1
PCIClk
na
na
na
na
na
na
async
PCIDevSel
30
6
1
0.5
1.5
PCIClk
1
PCIFrame
30
6
1
0.5
1.5
PCIClk
1
PCIGnt0/Req
PCIGnt1:2
na
na
6
1
0.5
1.5
PCIClk
1
PCIIDSel
3
0
nananana
PCIClk
1
PCIINT[PerWE]
na
na
na
na
0.5
1.5
PCIClk
1
PCIIRDY
30
6
1
0.5
1.5
PCIClk
1
PCIParity
3
0
6
1
0.5
1.5
PCIClk
1
PCIPErr
30
6
1
0.5
1.5
PCIClk
1
PCIReq0/Gnt
PCIReq1:2
5
0
na
na
na
na
PCIClk
1
PCIReset
na
na
na
na
0.5
1.5
PCIClk
1
PCISErr
na
na
na
na
0.5
1.5
PCIClk
1
PCIStop
30
6
1
0.5
1.5
PCIClk
1
PCITRDY
30
6
1
0.5
1.5
PCIClk
1
Ethernet Interface
EMC0MDClk
na
na
settable
2
10.3
7.1
async
2
EMC0MDIO
100
0
1 OPB clock
period + 10ns
1 OPB clock
period
10.3
7.1
EMC0MDClk
2
EMC0Tx0:1D3:0
na
na
14
5
10.3
7.1
PHY0TxClk
2
EMC0Tx0:1En
na
na
14
5
10.3
7.1
PHY0TxClk
2
EMC0Tx0:1Err
na
na
14
5
10.3
7.1
PHY0TxClk
2
PHY0Col0:1
2
3
na
na
na
na
PHY0RxClk
2
PHY0CrS0:1
2
3
na
na
na
na
PHY0RxClk
2
PHY0Rx0:1Clk
na
na
na
na
na
na
async
2
PHY0Rx0:1D3:0
2
4
na
na
na
na
PHY0RxClk
2
PHY0Rx0:1DV
2
4
nananana
PHY0RxClk
2
PHY0Rx0:1Err
2
4
na
na
na
na
PHY0RxClk
2
PHY0Tx0:1Clk
na
na
na
na
na
na
async
2



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