PPC440EP datasheet(12/84 Pages) AMCC

12 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Revision 1.26 – April 25, 2007

Data Sheet

External Peripheral Bus Controller (EBC)

Features include:

• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported

• Up to 66.66MHz operation

• Burst and non-burst devices

• 16-bit byte-addressable data bus

• 30-bit address

• Peripheral Device pacing with external “Ready”

• Latch data on Ready, synchronous or asynchronous

• Programmable access timing per device

– 256 Wait States for non-burst

– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses

– Programmable CSon, CSoff relative to address

– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS

• Programmable address mapping

• External DMA Slave Support

• External master interface

– Write posting from external master

– Read prefetching on PLB for external master reads

– Bursting capable from external master

– Allows external master access to all non-EBC PLB slaves

– External master can control EBC slaves for own access and control

Ethernet Controller Interface

Ethernet support provided by the PPC440EP interfaces to the physical layer but the PHY is not included on the

chip:

• One to two 10/100 interfaces running in full- and half-duplex modes

– One full Media Independent Interface (MII) with 4-bit parallel data transfer

– Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer

– Two Serial Media Independent Interfaces (SMII)

– Packet reject support

DMA to PLB 64 Controller

This DMA controller provides a DMA interface between the OPB and the 64-bit PLB.

Features include:

• Supports the following transfers:

– Memory-to-memory transfers

– Buffered peripheral to memory transfers

– Buffered memory to peripheral transfers

• Four channels

• Scatter/Gather capability for programming multiple DMA operations

• 32-byte buffer

• 8-, 16-, 32-bit peripheral support (OPB and external)

• 32-bit addressing

• Address increment or decrement

• Supports internal and external peripherals

• Support for memory mapped peripherals

• Support for peripherals running on slower frequency buses

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