HT49CV3 datasheet(13/44 Pages) HOLTEK

13 / 44 page

HT49RV3/HT49CV3

Rev. 1.30

March 20, 2007

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or an instruction clock

(system clock/4) or a real time clock oscillator (RTC os-

cillator). The timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The WDT can be

disabled by options. But if the WDT is disabled, all exe-

cutions related to the WDT lead to no operation.

Once an internal WDT oscillator (RC oscillator with a pe-

riod of 65

ms at 5V) is selected, it is divided by 212~215

(by configuration option to get the WDT time-out period).

The minimum WDT time-out period is 300ms~600ms.

This time-out period may vary with temperature, VDD

and process variations. By selecting the WDT configura-

tion option, longer time-out periods can be realized. If

the WDT time-out is selected, 2

15, the maximum

time-out period is divided by 2

15~216 which is 2.3s~4.7s.

If the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operates in the

same manner except that in the halt state the WDT may

stop counting and lose its protecting purposes. In this

situation the logic can only be restarted by external

logic. If the device operates in a noisy environment, us-

ing the on-chip RC oscillator (WDT OSC) is strongly rec-

ommended since the HALT will stop the system clock.

The WDT overflow under normal operation initializes a

²chip reset² and sets the status bit ²TO². In the HALT

mode, the overflow initializes a

²warm reset², and only

the Program Counter and SP are reset to zero. To clear

the contents of the WDT, there are three methods to be

adopted, i.e., external reset (a low level to RES), soft-

ware instruction, and a

²HALT² instruction. There are

two types of software instructions;

²CLR WDT² and the

other set

-²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one type of instruction can

be active at a time depending on the options

-²CLR

WDT

² times selection option. If the ²CLR WDT² is se-

lected (i.e., CLR WDT times is equal to one), any execu-

tion of the

²CLR WDT² instruction clears the WDT. In the

case where the two

²CLR WDT1² and ²CLR WDT2² in-

structions are chosen (i.e., CLR WDT times is equal to

two), these two instructions have to be executed to clear

the WDT, otherwise, the WDT may reset the chip due to

time-out.

Multi-function Timer

The HT49RV3/HT49CV3 provides a multi-function timer

for the WDT and RTC but with different time-out periods.

The multi-function timer consists of an 8-stage divider

and a 7-bit prescaler, with the clock source coming from

the RTC OSC or the instruction clock (i.e., system clock

divided by 4). The multi-function timer also provides a

selectable frequency signal (ranging from fS/2

0 to f

S/2

for the VFD driver circuits, and a selectable frequency

signal (ranging from fS/2

1 to f

S/2

8) for the buzzer output

by options. It is recommended to select a frequency as

close as possible to 32kHz for the VFD driver circuits to

obtain good display clarity.

Real Time Clock

- RTC

The real time clock (RTC) is used to supply a regular in-

ternal interrupt. Its time-out period ranges from fS/2

8 to

fS/2

15 by software programming. Writing data to RT2,

RT1 and RT0 (bits 2, 1, 0 of RTCC; 09H) yields various

time-out periods. If the RTC time-out occurs and the in-

terrupt is enabled, the related interrupt request flag

(RTF; bit 1 of the MFIS) is set and the multi-function in-

terrupt request flag (MFF; bit 6 of the INTC1) is set. If the

interrupt (EMFI) is enabled, and the stack is not full, a

subroutine call to location 18H occurs.

RT2

RT1

RT0

RTC Clock Divided Factor

000

001

010

10*

011

11*

100

101

110

111

Note: * not recommended to be used

T i m e - o u t R e s e t

f W D T / 2 1 5 ~ f W D T / 2 1 6

f W D T / 2 1 4 ~ f W D T / 2 1 5

f W D T / 2 1 3 ~ f W D T / 2 1 4

f W D T / 2 1 2 ~ f W D T / 2 1 3

D i v i d e r

W D T C l e a r

C o n f i g u r a t i o n

O p t i o n

W D T

O S C 1 2 k H z

C K T

W D T

P r e s c a l e r

M a s k O p t i o n

f W D T / 2 8

S y s t e m C l o c k / 4

C o n f i g u r a t i o n

O p t i o n

R T C

O S C 3 2 7 6 8 H z

f S

f W D T

Watchdog Timer

D i v i d e r

f S

R O M C o d e O p t i o n

V F D D r i v e r ( f S / 2 0 ~ f S / 2 7 )

B u z z e r ( f S / 2 1 ~ f S / 2 8 )

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