DSP56321 datasheet(34/84 Pages) FREESCALE

34 / 84 page

DSP56321 Technical Data, Rev. 11

2-14

Freescale Semiconductor

Specifications

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These

synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this

delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the

reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other

DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG

is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time.

Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251

ensures that overlaps are avoided.

2.4.6

Host Interface Timing

Figure 2-12.

Asynchronous Bus Arbitration Timing

Table 2-10.

Host Interface Timings1,2,12

No.

Characteristic10

Expression

200 MHz

220 MHz

240 MHz

275 MHz

Uni

Min

Max

Min

Max

Min

Max

Min

Max

317

Read data strobe assertion width

HACK assertion width

TC + 4.95

9.95

—

9.05

—

8.3

—

7.77

—

318

Read data strobe deassertion width5

HACK deassertion width

4.95

—

4.5

—

4.13

—

4.0

—

319

Read data strobe deassertion width5 after

“Last Data Register” reads8,11, or between two

consecutive CVR, ICR, or ISR reads

HACK deassertion width after “Last Data

2.5

× T

C + 3.3

15.8

—

14.7

—

13.7

—

12.39

—

320

Write data strobe assertion width

6.6

—

6.0

—

5.5

—

5.1

—

321

Write data strobe deassertion width8

HACK write deassertion width

•

after ICR, CVR and “Last Data Register”

writes

•

after IVR writes, or

after TXH:TXM:TXL writes (with HLEND=

0), or

after TXL:TXM:TXH writes (with HLEND =

2.5

× TC + 3.3 15.8

8.25

—

14.7

7.5

—

13.7

6.88

—

12.39

6.28

—

322

HAS assertion width

4.95

—

4.5

—

4.13

—

4.0

—

BG1

251

BG2

250

250+251

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