FS32K118LAT0MLHT datasheet(32/84 Pages) NXP

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System Clock Generation (SCG) specifications

6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications

Table 19. Fast internal RC Oscillator electrical specifications

Symbol

Parameter1

Value

Unit

Min.

Typ.

Max.

FFIRC

FIRC target frequency

—

MHz

ΔF

Frequency deviation across process, voltage, and

temperature < 105°C

—

±0.5

±1

%FFIRC

ΔF125

Frequency deviation across process, voltage, and

temperature < 125°C

—

±0.5

±1.1

%FFIRC

TStartup

Startup time

3.4

µs2

TJIT, 3

Cycle-to-Cycle jitter

—

300

500

TJIT3

Long term jitter over 1000 cycles

—

0.04

0.1

%FFIRC

1. With FIRC regulator enable

2. Startup time is defined as the time between clock enablement and clock availability for system use.

3. FIRC as system clock

NOTE

Fast internal RC oscillator is compliant with LIN when device

is used as a slave node.

6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications

Table 20. Slow internal RC oscillator (SIRC) electrical specifications

Symbol

Parameter

Value

Unit

Min.

Typ.

Max.

FSIRC

SIRC target frequency

—

MHz

ΔF

Frequency deviation across process, voltage, and

temperature < 105°C

—

±3

%FSIRC

ΔF125

Frequency deviation across process, voltage, and

temperature < 125°C

—

±3.3

%FSIRC

TStartup

Startup time

—

12.5

µs1

1. Startup time is defined as the time between clock enablement and clock availability for system use.

6.2.3

System Clock Generation (SCG) specifications

S32K1xx Data Sheet, Rev. 9, 09/2018

NXP Semiconductors

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