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DSP56721 Arkusz danych(PDF) 34 Page - Freescale Semiconductor, Inc |
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DSP56721 Arkusz danych(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 54 page ![]() SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 34 Figure 26. Test Clock Input Timing Diagram Figure 27. Debugger Port Timing Diagram 116 TMS, TDI data setup time 5.0 – ns 117 TMS, TDI data hold time 25.0 – ns 118 TCK low to TDO data valid – 44.0 ns 119 TCK low to TDO high impedance – 44.0 ns Notes: 1. VCORE_VDD = 1.0 V ± 0.10 V; TJ = -40°C to 125°C , CL = 50 pF 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. Table 16. JTAG Timing Parameters (Continued) No. Characteristics All Frequencies Unit Min Max 109 110 110 111 111 TCK (Input) VIL VM VIH VM VIH VIL 113 112 114 115 114 TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs Input Data Valid Output Data Valid Output Data Valid |
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