S25FL128SDPNFAQ datasheet(29/149 Pages) CYPRESS

Numer części	S25FL128SDPNFAQ

Szczegółowy opis	128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)

PDF	149 Pages

Scroll/Zoom	100%

Producent	CYPRESS [Cypress Semiconductor]

Strona internetowa	http://www.cypress.com

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29 / 149 page

Document Number: 001-98283 Rev. *M

Page 28 of 148

S25FL128S/S25FL256S

Timing Specifications

5.1

Key to Switching Waveforms

Figure 23. Waveform Element Meanings

Figure 24. Input, Output, and Timing Reference Levels

5.2

AC Test Conditions

Figure 25. Test Setup

Notes:

1. Output High-Z is defined as the point where data is no longer driven.

2. Input slew rate: 1.5 V/ns.

3. AC characteristics tables assume clock and data signals have the same slew rate (slope).

4. DDR Operation.

Table 9. AC Measurement Conditions

Symbol

Parameter

Min

Max

Unit

Load Capacitance

15 (4)

Input Rise and Fall Times

2.4

Input Pulse Voltage

0.2 x VIO to 0.8 VIO

Input Timing Ref Voltage

0.5 VIO

Output Timing Ref Voltage

0.5 VIO

Input

Symbol

Output

Valid at logic high or low

High Impedance

Any change permitted

Logic high Logic low

Valid at logic high or low

High Impedance

Changing, state unknown Logic high Logic low

VIO + 0.4V

0.7 x VIO

0.2 x VIO

- 0.5V

Timing Reference Level

0.5 x VIO

0.85 x VIO

0.15 x VIO

Input Levels

Output Levels

Device

Under

Test

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