 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
S25FL128SDPNFAQ Arkusz danych(PDF) 52 Page - Cypress Semiconductor |
|
|
|||||||||||||||||||||||||||||
S25FL128SDPNFAQ Arkusz danych(HTML) 52 Page - Cypress Semiconductor |
|
|
52 / 149 page  Document Number: 001-98283 Rev. *M Page 51 of 148 S25FL128S/S25FL256S Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the start of read data, if there are 5 or more dummy cycles. See Section 9.4 Read Memory Array Commands on page 84 for more information on the DLP. Note: 1. When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP. It is recommended to use LC 10 for DDR Fast Read, LC 01 for DDR Dual IO Read, and LC 00 for DDR Quad IO Read, if the Data Learning Pattern (DLP) for DDR is used. Table 26. Latency Codes for SDR High Performance Freq. (MHz) LC Read Fast Read Read Dual Out Read Quad Out Dual I/O Read Quad I/O Read (03h, 13h) (0Bh, 0Ch) (3Bh, 3Ch) (6Bh, 6Ch) (BBh, BCh) (EBh, ECh) Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy ≤ 50 11 0000000004 21 ≤ 80 00 - - 08080804 24 ≤ 90 01 - - 08080805 24 ≤104 10 - - 08080806 25 ≤133 10 - - 0 8 ------ -- Table 27. Latency Codes for DDR High Performance Freq. (MHz) LC DDR Fast Read DDR Dual I/O Read Read DDR Quad I/O (0Dh, 0Eh) (BDh, BEh) (EDh, EEh) Mode Dummy Mode Dummy Mode Dummy ≤ 50 11 04 041 3 ≤ 66 00 05 061 6 ≤ 66 01 06 071 7 ≤ 66 10 07 081 8 Table 28. Latency Codes for SDR Enhanced High Performance Freq. (MHz) LC Read Fast Read Read Dual Out Read Quad Out Dual I/O Read Quad I/O Read (03h, 13h) (0Bh, 0Ch) (3Bh, 3Ch) (6Bh, 6Ch) (BBh, BCh) (EBh, ECh) Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy ≤ 50 11 0 00000 004021 ≤ 80 00 - - 0808 084024 ≤ 90 01 - - 0808 084124 ≤104 10 - - 0808 084225 ≤133 10 - - 0 8 - - ------ Table 29. Latency Codes for DDR Enhanced High Performance Freq. (MHz) LC DDR Fast Read DDR Dual I/O Read Read DDR Quad I/O (0Dh, 0Eh) (BDh, BEh) (EDh, EEh) Mode Dummy Mode Dummy Mode Dummy ≤ 50 11 41 221 3 ≤ 66 00 42 241 6 ≤ 66 01 44 251 7 ≤ 66 10 45 261 8 ≤ 80 00 42 241 6 ≤ 80 01 44 251 7 ≤ 80 10 45 261 8 |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
