TIMING INFORMATION

t

HD, STA

t

SU, DAT

t

HD, DAT

t

SU, STA

t

SU, STO

t

HD, STA

t

LOW

t

HIGH

t

R

t

F

t

BUF

SDA

START

CONDITION

START

CONDITION

STOP

CONDITION

REPEATED

START

CONDITION

SCL

TIMING REQUIREMENTS: I

2C Standard Mode (SCL = 100kHz)

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009...................................................................................................................................................... www.ti.com

Figure 1. Detailed I/O Timing

All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.

2-WIRE STANDARD MODE PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SCL clock frequency

fSCL

0

100

kHz

Bus free time between a STOP and START condition

tBUF

4.7

µs

Hold time (repeated) START condition

tHD, STA

4.0

µs

Low period of SCL clock

tLOW

4.7

µs

High period of the SCL clock

tHIGH

4.0

µs

Setup time for a repeated START condition

tSU, STA

4.7

µs

Data hold time

tHD, DAT

0

3.45

µs

Data setup time

tSU, DAT

250

ns

Rise time for both SDA and SCL signals (receiving)

tR

Cb = total bus capacitance

1000

ns

Fall time for both SDA and SCL signals (receiving)

tF

Cb = total bus capacitance

300

ns

Fall time for both SDA and SCL signals (transmitting)

tF

Cb = total bus capacitance

250

ns

Setup time for STOP condition

tSU, STO

4.0

µs

Capacitive load for each bus line

Cb

Cb = total capacitance of one bus line in pF

400

pF

8 bits

40 SCL + 127 CCLK, VDD = 1.8V

434.7

µs

Cycle time

12 bits

49 SCL + 148 CCLK, VDD = 1.8V

570.9

µs

8 bits

VDD = 1.8V

2.3

kSPS

Effective throughput

12 bits

VDD = 1.8V

1.75

kSPS

8 bits

VDD = 1.8V

16.1

kHz

Equivalent rate = effective throughput × 7

12 bits

VDD = 1.8V

12.26

kHz

6

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