LP5521TM datasheet(16/51 Pages) TI2

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Input

Buffer

Level

Shifter

Level

Shifter

SDA

SCL

VDD

LP5521

SNVS441I – JANUARY 2007 – REVISED NOVEMBER 2016

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Table 7. CONFIG Register (08H):

NAME

BIT

DESCRIPTION

CLK_DET_EN,

INT_CLK_EN

1:0

LED controller clock source

00b = External clock source (CLK_32K)

01b = Internal clock

10b = Automatic selection

11b = Internal clock

7.3.5 Logic Interface Operational Description

LP5521 features a flexible logic interface for connecting to processor and peripheral devices. Communication is

done with I2C compatible interface and different logic input/output pins makes it possible to synchronize

operation of several devices.

7.3.5.1 I/O Levels

I2C interface, CLK_32K and TRIG pins input levels are defined by EN pin. Using EN pin as voltage reference for

logic inputs simplifies PWB routing and eliminates the need for dedicated VIO pin. Figure 17 describes EN pin

connections.

Figure 17. Using EN Pin as Digital I/O Voltage Reference

ADDR_SEL0/1 are referenced to VDD voltage. GPO pin level is defined by VDD voltage.

7.3.5.2 GPO/INT Pins

LP5521 has one General Purpose Output pin (GPO); the INT pin can also be configured as a GPO pin. When

INT is configured as GPO output, its level is defined by the VDD voltage. State of the pins can be controlled with

GPO register (0EH). GPO pins are digital CMOS outputs and no pullup or pulldown resistors are needed.

When INT pin GPO function is disabled, it operates as an open drain pin. INT signal is active low; that is, when

interrupt signal is sent, the pin is pulled to GND. External pullup resistor is needed for proper functionality.

Table 8. GPO Register (0EH)

NAME

BIT

DESCRIPTION

INT_AS_GPO

Enable INT pin GPO function

0 = INT pin functions as a INT pin

1 = INT pin functions as a GPO pin

GPO

0 = GPO pin state is low

1 = GPO pin state is high

INT

0 = INT pin state is low (INT_AS_GPO=1)

1 = INT pin state is high (INT_AS_GPO=1)

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