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TLV702 Arkusz danych(PDF) 4 Page - Texas Instruments |
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TLV702 Arkusz danych(HTML) 4 Page - Texas Instruments |
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4 / 36 page ![]() OUT NC IN GND EN 1 2 3 5 4 EN N/C N/C 6 5 4 IN GND OUT 1 2 3 4 TLV702-Q1 SLVSC35D – AUGUST 2013 – REVISED JULY 2019 www.ti.com Product Folder Links: TLV702-Q1 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated 5 Pin Configuration and Functions DDC and DBV Package 5-pin SOT Top View DSE Package 6-Pin WSON Top View Pin Functions PIN I/O DESCRIPTION NAME DDC, DBV (SOT) DSE (WSON) IN 1 1 I Input pin. A small, 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. See Input and Output Capacitor Requirements in the Application Information section for more details. GND 2 2 — Ground pin EN 3 6 I Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode and reduces operating current to 1 μA, nominal. NC 4 4, 5 — No connection. Tie this pin to ground to improve thermal dissipation. OUT 5 3 O Regulated output voltage pin. A small, 1-μF ceramic capacitor is needed from this pin to ground for stability. See Input and Output Capacitor Requirements in the Application Information section for more details. |
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