STA381BWS_V01 datasheet(90/174 Pages) STMICROELECTRONICS

90 / 174 page

STA381BWS

90/174

DocID018937 Rev 7

6.27

PLL configuration registers (address 0x52; 0x53; 0x54; 0x55;

0x56; 0x57)

By default, the STA381BWS is able to configure the embedded PLL automatically

depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to

the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’)

The output PLL frequency formula is:

where Fin is the input clock frequency from the pad.

PLL_FRAC[15:8]

00000000

PLL_FRAC[7:0]

00000000

PLL_DITH[1:0]

PLL_NDIV[5:0]

00000000

PLL_DPD

PLL_FCT

PLL_STB

PLL_STBBYP

PLL_IDIV[3:0]

00000000

Reserved

PLL_DIRP

PLL_PWD

PLL_BYP

OSC_PD

Reserved

BOOST32K

00000000

Reserved

BYPSTATE

PDSTATE

OSCOK

LOWCK

Table 80. PLL factors

PLL parameter

Min

Max

FRAC

65535

IDIV

NDIV

Fin

NDIV



IDIV 1



---------------------------

FRAC

65536

-----------------











Obsolete

Product(s)

- Obsolete

Product(s)

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