IS25LP02GJ-RHLA3 datasheet(67/182 Pages) ISSI

67 / 182 page

IS25LP02GJ

IS25WP02GJ

Integrated Silicon Solution, Inc.- www.issi.com

Rev.A

10/02/2025

Figure 8.9 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=0], 3-byte address)

CE#

SCK

3-byte Address

...

Mode 3

Mode 0

...

IO0

IO1

4 Dummy Cycles

Data Out 1

Mode Bits

...

Data Out 2

...

Notes:

1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

Figure 8.10 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=1] or BCh, 4-byte address)

CE#

SCK

4-byte Address

...

Mode 3

Mode 0

...

IO0

IO1

4 Dummy Cycles

Data Out 1

Mode Bits

...

Data Out 2

...

Notes:

1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

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