MPC7447A datasheet(39/60 Pages) FREESCALE

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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Freescale Semiconductor

System Design Information

Figure 17. MPC7448 Power Down Sequencing Requirements

There is no requirement regarding AVDD during power down, but it is recommended that AVDD track VDD

within the RC time constant of the PLL filter circuit described in Section 9.2.2, “PLL Power Supply

Filtering” (nominally 100 µs).

9.2.2

PLL Power Supply Filtering

The AVDD power signal is provided on the MPC7448 to provide power to the clock generation PLL. To

ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any

noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. The circuit shown in Figure 18

using surface mount capacitors with minimum effective series inductance (ESL) is strongly recommended.

In addition to filtering noise from the AVDD input, it also provides the required delay between VDD and

AVDD as described in Section 9.2.1, “Power Supply Sequencing.”

The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby

circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery

of the device footprint.

Figure 18. PLL Power Supply Filter Circuit

VDD

OVDD

no restrictions between VDD and OVDD

SYSCLK

0.9 V

AVDD

no restrictions between VDD and AVDD

note also restrictions between SYSCLK and OVDD

0.9 V

limit imposed by VDD if VDD ramps down first

limit imposed by OVDD if OVDD ramps down first

VDD

AVDD

2.2 µF

GND

Low ESL Surface Mount Capacitors

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