STA328 datasheet(16/41 Pages) STMICROELECTRONICS

16 / 41 page

STA328

16/41

Figure 13.

7.3.1

Delay Serial Clock Enable

7.3.2

Channel Input Mapping

Each channel received via I2S can be mapped to any internal processing channel via the Channel Input

Mapping registers. This allows for flexibility in processing. The default settings of these registers map

each I2S input channel to its corresponding processing channel.

7.4 CONFIGURATION REGISTER C (Address 02h)

7.4.1

DDX® Power Output Mode

The DDX® Power Output Mode selects how the DDX® output timing is configured. Different power de-

vices can use different output modes. The DDX-2060/2100/2160 recommended use is OM = 10. When

OM=11 the CSZ bits determine the size of the DDX® compensating pulse.

BIT

R/W

RST

NAME

DESCRIPTION

R/W

DSCKE

Delay Serial Clock Enable:

0 – No serial clock delay

1 – Serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

BIT

R/W

RST

NAME

DESCRIPTION

6R/W

C1IM

0 – Processing channel 1 receives Left I2S Input

1 – Processing channel 1 receives Right I2S Input

7R/W

C2IM

0 – Processing channel 2 receives Left I2S Input

1 – Processing channel 2 receives Right I2S Input

CSZ4

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

000

BIT

R/W

RST

NAME

DESCRIPTION

1...0

R/W

OM (1...0)

DDX Power Output Mode:

Selects configuration of DDX® output.

BICKI

LRCKI

SDI

STA328 Arkusz danych(PDF) 16 Page - STMicroelectronics

STA328 Arkusz danych(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Arkusz danych Pobierz

Link URL