MSC8103SLASHD datasheet(99/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

4-1

Design Considerations

This chapter includes design and layout guidelines for manufacturing boards using the MSC8103.

4.1 Thermal Design Considerations

The average chip-junction temperature, TJ, in ° C can be obtained from the following:

TJ = TA + (PD • θJA)

Equation 1

where

TA = ambient temperature ° C

JA = package thermal resistance, junction to ambient, ° C/W

PD = PINT + PI/O in W

PINT = IDD × VDD in W—chip internal power

PI/O = power dissipation on output pins in W—user determined

The user should set TA and PD such that TJ does not exceed the maximum operating conditions. In case TJ is too

high, the user should either lower the ambient temperature or the power dissipation of the chip.

4.2 Electrical Design Considerations

The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on

reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms.

VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH

by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use

“bootstrap” diodes between the power rails, as shown in Figure 4-1.

Figure 4-1.

Bootstrap Diodes for Power-Up Sequencing

I/O Power

Core/PLL

Supply

MUR420

3.3 V (VDDH)

1.6 V (VDD/VCCSYN)

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