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STM32F103X8 Arkusz danych(PDF) 32 Page - STMicroelectronics |
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STM32F103X8 Arkusz danych(HTML) 32 Page - STMicroelectronics |
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32 / 84 page ![]() Electrical characteristics STM32F103xx 32/84 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 9 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 9. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit VPVD Programmable voltage detector level selection PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V VPVDhyst (2) PVD hysteresis 100 mV VPOR/PDR Power on/power down reset threshold Falling edge 1.8(1) 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 1.88 1.96 V Rising edge 1.84 1.92 2.0 V VPDRhyst PDR hysteresis 40 mV TRSTTEMPO (2) 2. Guaranteed by design, not tested in production. Reset temporization 1 2.5 4.5 mS |
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