ST7LITE1XB datasheet(89/157 Pages) STMICROELECTRONICS

89 / 157 page

ST7LITE1xB

89/157

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits (See

Figure 57).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if

CPOL = 0).

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture

clock edge.

Figure 57 shows an SPI transfer with the four com-

binations of the CPHA and CPOL bits. The dia-

gram may be interpreted as a master or slave tim-

ing diagram where the SCK pin, the MISO pin and

the MOSI pin are directly connected between the

master and the slave device.

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Figure 57. Data Clock Timing Diagram

SCK

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPHA = 1

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(to slave)

CAPTURE STROBE

CPHA = 0

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

(from slave)

(CPOL = 1)

SCK

(CPOL = 0)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

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